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Sheet目录3887

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2003 Microchip Technology Inc.

DS30569B-page 85

PIC16F870/871

10.5

A/D Operation During SLEEP

The A/D module can operate during SLEEP mode. This

requires that the A/D clock source be set to RC

(ADCS1:ADCS0 = 11). When the RC clock source is

selected, the A/D module waits one instruction cycle

before starting the conversion. This allows the SLEEP

instruction to be executed, which eliminates all digital

switching noise from the conversion. When the conver-

sion is completed, the GO/DONE bit will be cleared and

the result loaded into the ADRES register. If the A/D

interrupt is enabled, the device will wake-up from

SLEEP. If the A/D interrupt is not enabled, the A/D mod-

ule will then be turned off, although the ADON bit will

remain set.

When the A/D clock source is another clock option (not

RC), a SLEEP instruction will cause the present conver-

sion to be aborted and the A/D module to be turned off,

though the ADON bit will remain set.

Turning off the A/D places the A/D module in its lowest

current consumption state.

10.6

Effects of a RESET

A device RESET forces all registers to their RESET

state. This forces the A/D module to be turned off, and

any conversion is aborted. All A/D input pins are

configured as analog inputs.

The value that is in the ADRESH:ADRESL registers is

not

modified

for

Power-on

Reset.

The

ADRESH:ADRESL registers will contain unknown data

after a Power-on Reset.

TABLE 10-2:

REGISTERS/BITS ASSOCIATED WITH A/D

Note:

For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC

(ADCS1:ADCS0 = 11). To allow the con-

version to occur during SLEEP, ensure the

SLEEP

instruction immediately follows the

instruction that sets the GO/DONE bit.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

MCLR,

WDT

0Bh,8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

—

CCP1IF

TMR2IF

TMR1IF

0000 -000

8Ch

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

—

CCP1IE

TMR2IE TMR1IE 0000 -000 0000 -000

1Eh

ADRESH

A/D Result Register High Byte

xxxx xxxx

uuuu uuuu

9Eh

ADRESL

A/D Result Register Low Byte

xxxx xxxx

uuuu uuuu

1Fh

ADCON0

ADCS1

ADCS0

CHS2

CHS1

CHS0

GO/DONE

—ADON

0000 00-0

9Fh

ADCON1

ADFM

—

—PCFG3

PCFG2

PCFG1

PCFG0

--0- 0000

85h

TRISA

—

PORTA Data Direction Register

--11 1111

05h

PORTA

—

PORTA Data Latch when written: PORTA pins when read

--0x 0000

--0u 0000

89h(1)

TRISE

IBF

OBF

IBOV

PSPMODE

—

PORTE Data Direction bits

0000 -111

09h(1)

PORTE

—

RE2

RE1

RE0

---- -xxx

---- -uuu

Legend:

= unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.

Note

These registers/bits are not available on the 28-pin devices.

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